The present invention generally relates to forming dual damascene structures in semiconductor substrates. In particular, the present invention relates to efficiently forming dual damascene structures in a single layer of insulation material without the need for a trench etch stop layer.
Conventional semiconductor devices typically comprise a semiconductor substrate and a plurality of dielectric and conductive layers formed thereon. An integrated circuit contains numerous microelectronic devices, such as metal oxide semiconductor field effect transistors (MOSFETs), a plurality of conductive patterns comprising conductive lines separated by interwiring spacings, and a plurality of interconnect lines, such as bus lines, bit lines, word lines and logic interconnect lines. Such interconnection lines, made of metal interconnect materials, generally constitute a limiting factor in terms of size (width) and various functional characteristics of the integrated circuit. As such, there exists a need to efficiently provide a reliable interconnection structure having a small size yet capable of achieving higher operating speeds, improved signal-to-noise ratio and improved reliability.
Using a dual damascene process, semiconductor devices are patterned with several thousand openings for conductive lines and vias which are filled with a conductive metal, such as aluminum or copper, and serve to interconnect the active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming the multilevel signal lines of conductive metal in the insulating layers of multilayer substrate on which semiconductor devices are mounted.
Damascene (single damascene) is an interconnection fabrication process in which grooves are formed in an insulating structure and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, the conductive via openings also are formed.
In the standard dual damascene process, a first mask with the image pattern of the via openings is formed over the insulating structure and the wafer is anisotropically etched in the upper portion of the insulating structure (via etch). After removal of the patterned resist material, a second mask is formed over the insulating structure with the image pattern of the conductive lines in alignment with the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched in the lower half of the insulating material (trench etch). After the etching is complete, both the vias and grooves are filled with metal. This process is illustrated in FIG. 1.
In another standard dual damascene process, a first mask is formed over the insulating structure with the image pattern of the via openings and the pattern is anisotropically etched in the insulating structure (via etch). After removal of the patterned resist material, a second mask is formed over the insulating structure with the image pattern of the conductive lines in alignment with the via openings and the pattern of the conductive lines is anisotropically etched (trench etch). After the etching is complete, both the vias and grooves are filled with metal. This process is illustrated in FIG. 2.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps. Although standard dual damascene offers advantages over other processes for forming interconnections, it has a number of disadvantages. For example, the insulating structure through which vias and trenches are formed is typically comprised of three layers; namely, relatively thick lower and an upper insulating layers of a first material sandwiching a relatively thin insulating layer of a second material where there is etch selectivity between the first material and the second material. The relatively thin insulating layer is also known as the trench etch stop layer. The presence of the relatively thin insulating layer thus improves the ability to accurately and precisely terminate the trench etch so that the depths of the trenches correspond with the desired depth.
The use of multilayered insulating structures complicates processing due to the requirement of forming multiple layers of precise thickness. However, in the absence of the trench etch stop layer, performing the trench etch leads to trenches that are too shallow or too deep, and poor uniformity across the wafer (such as trenches that are too shallow in regions near the edges of the wafer and trenches that are too deep in the center of the wafer). Moreover, trench etch performance varies from wafer to wafer.
The present invention provides systems and methods for improving dual damascene processes by eliminating the requirement of using a trench etch stop layer. In this connection, the systems and methods for employing dual damascene processes employ a single layer insulating structure that is simple to fabricate. The systems and methods employ the use of a monitoring system capable of monitoring trench etch depth and profile over the entire wafer during the etch trench process, thereby enabling an operator to accurately terminate the trench etch process.
One aspect of the present invention relates to a method of dual damascene processing involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material, wherein groups of via openings are positioned in a substantially straight line; and simultaneously (i) forming a plurality of trenches in the insulation structure, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system by generating a signature associated with forming the trenches, comparing the signature to a signature library to determine trench depth, and terminating forming the trenches when a desired trench depth is attained.
Another aspect of the present invention relates to a method of forming a dual damascene opening in a semiconductor substrate involving providing a semiconductor substrate with an insulation structure on an upper surface thereof, the insulation structure containing a single layer of a dielectric material; forming at least one via opening in the insulation structure; and simultaneously (i) forming a trench in the insulation structure, the trench positioned above the via opening, both the via opening and the trench constituting the dual damascene opening, and (ii) monitoring forming the trench using a scatterometry system by: directing a beam of incident light at the insulation structure, collecting light reflected from the insulation structure, transforming the reflected light into a signature associated with forming the trench, comparing the signature to a signature library to determine trench depth, and terminating forming the trench when a desired trench depth is attained.
Yet another aspect of the present invention relates to a method of forming a dual damascene structure involving forming a plurality of via openings in the insulation structure containing a single layer of a dielectric material, wherein groups of via openings are positioned in a substantially straight line; simultaneously (i) forming a plurality of trenches in the insulation structure using a trench etch controller, each trench positioned along the substantially straight line of a group of via openings, and (ii) monitoring the formation of trenches using a scatterometry system by generating a signature associated with forming the trenches, comparing the signature to a signature library to determine trench depth, and if the determine trench depth is not within an acceptable range of desired trench depths, instructing the trench etch controller to continue forming the trenches and optionally adjust a trench etch process component; and if the determine trench depth is within an acceptable range of desired trench depths, instructing the trench etch controller to terminate forming the trenches.